High Reliability Bumping Process and WLP Total Service

LB Semicon Inc. is a total solution company in the Outsourced Semiconductor Assembly & Test (OSAT) field that provides customers with full turnkey service.
Founded in 2000, LB Semicon started its business providing Au process service for DDI products to domestic fabless companies. In line with the advent of mobile products, it has expanded the product portfolio to satisfy the demands of leading domestic and foreign fabless.
LB Semicon provides full turnkey assembly solutions that include DPS and wafer-level probe testing. The company has completed all the preparations to enter the FOWLP market, which is expected to grow further in the future.
“Striving to be the best worldwide, we will become a leading global OSAT company by providing our own unique SiP products in the market, ” stressed the company’s president.

Wafer-level packaging
Wafer-level Packaging (WLCSP) is the technology of packaging and testing an integrated circuit while at the wafer level and then slicing it into chips to make the completed product, which differs from the conventional method of slicing the processed wafer first into individual chips and then packaging them. WLCSP is true chip-scale packaging technology.
Demand for WLCSP is increasing rapidly in the mobile market, due to the realization of a true chip-scale package with excellent electrical properties and price competitiveness. The WLCSP continues to expand its scope of application. LB Semicon currently provides various layers of WLCSP solutions ranging from two layers to six layers tailored to meet the needs of its customers. WLCSP is applied at PMIC, RF & BB SoC, transceivers, AOC, and sensors.

Fan-out wafer-level packaging
FOWLP is composed of epoxy mold compound (EMC). This technology eliminates the need for printed circuit boards in LB Semicon’s packages by directly forming the redistribution layer and solder balls on top of the EMC. FOWLP’s applications include PMIC and RFIC.

Cu pillar bumping
As semiconductor devices are rapidly becoming more integrated and faster, chips’ I/O density is increasing at a rapid pace while the bump pitch is continuously decreasing. Cu pillar is a bumping technology, developed to meet such needs for fine pitches, and it can accomplish much finer pitch of 40um or smaller, compared to the 150um level that existing solder bumping method could reach.

Cu pillar is currently being applied to various packages and its application will be expanded even more because of its excellent thermal dissipation performance and electro-migration properties, compared to solder bumping. Cu pillar bumping is used in fcBGA & fcQFN PKG, BB & AP processors, power amplifiers, NAND flash, and Wi-Fi modules.
 
 
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